VDC I/O Ports and Registers.

videoport = $0000

VDC port

video_reg = videoport

VDC register latch

• Writing the lower five bits of video_reg $0000 selects which register will be accessed at video_data_l ($0002) and video_data_h ($0003).  Only registers $00 to $02 and $05 to $13 are valid; selecting registers $03, $04 or $14 to $1F and trying to access them has no effect (see VDC registers).
• Reading video_reg $0000 returns a set of status flags (see VDC status flags).

video_data = videoport+2

VDC data

Data to be read or written to the a VDC register.

VDC_STATUS_SPR_COLLISION = %00000001

Set when the sprite #0 collision detection interrupt occurs.  The collision happens if any of the opaque pixel of sprite #0 is overlapping any other sprites.

VDC_STATUS_SPR_OVERFLOW = %00000010

Set when the sprite overflow interrupt occurs.  More precisely, when there are more than 16 sprites on a scanline.

VDC_STATUS_HBLANK = %00000100

Set when the horizontal blank interrupt occurs.  This interrupt is triggered when the scanline matches the value stored in VDC register $06.

VDC_STATUS_SATB_DMA_END = %00001000

Set when the VRAM to SATB DMA transfer completion interrupt occurs.

VDC_STATUS_VRAM_DMA_END = %00010000

Set when the VRAM to VRAM DMA transfer completion interrupt occurs.

VDC_STATUS_VBLANK = %00100000

Set when the vertical blank interrupt occurs.

VDC_STATUS_BUSY = %01000000

Set when the VDC is waiting for a CPU access slot during the active display area.

VDC_MAWR = $00

Memory Address Write Register

Detail

Set the word offset in VRAM where data written to VDC_DATA will be stored.  The value of this register is automatically incremented after a write to the MSB of VDC_DATA.  The increment value is set via bits 11 and 12 of VDC_CR.

VDC_MARR = $01

Memory Address Read Register

Detail

Set the word offset in VRAM from where data will be read.  Just like VDC_MAWR, this register is automatically incremented after a read to the high byte of VDC_DATA and the increment is set via bits 11 and 12 of VDC_CR.

VDC_DATA = $02

VRAM Data register

Detail

• Writing to LSB (video_data_l), the CPU data is stored in the write latch.  When the MSB is written (video_data_h), the whole 16 bits from the write latch and the MSB are transfered to the memory location set with VDC_MAWR.  VDC_MAWR is then automatically incremented according to the value set in the control register VDC_CR.
• Reading the LSB (video_data_l) will store the LSB of the read buffer, and reading the MSG (video_data_h) will store the MSB of the read buffer.  VDC_MARR is then incremented by the factor set in VDC_CR, and a word is read of VRAM at the location set by VDC_MARR is read and stored in the read buffer.

VDC_CR = $05

Control Register

Detail

Enables or disables VDC interrupts, background or sprite display, and set the read and write auto-increment.  See Control Register Flags for a complete description.

Value

VDC_RCR = $06

Raster Compare Register

Detail

Set the scanline on which the horizontal scanline interrupt should be raised.  The first scanline of the display area is the number 64.  Valid RCR register values range from 64 to 326.

Value

VDC_BXR = $07

Background X Scroll Register

Detail

Horizontal screen position in the virtual background map.

Value

VDC_BYR = $08

Background Y Scroll Register

Detail

Vertical screen position in the virtual background map.

Value

VDC_MWR = $09

Memory Width Register (MWR)

Detail

Set virtual background map size.

Value

VDC_HSR = $0A

Horizontal Synchro Register

Detail

Set horizontal synchro width and start position.

Value

VDC_HDR = $0B

Horizontal Display Register

Detail

Set horizontal display width and end position.

Value

VDC_VSR = $0C

Vertical Synchro Register

Detail

Set vertical synchro width and start position.

Value

VDC_VDR = $0D

Vertical Display Register

Detail

Set vertical display width.

Value

VDC_VCR = $0E

Vertical Display End Position Register

Value

VDC_DMA_CR = $0F

DMA Control Register

Detail

Enables or disables VRAM to VRAM or VRAM to SATB end of transfer interrupts.  Set source and destination direction (increment or decrement), and enable or disable SATB DMA automatic transfer (see DMA Control Register Flags).

Value

VDC_DMA_SRC = $10

DMA Source Address Register

VDC_DMA_DST = $11

DMA Destination Address Register

VDC_DMA_LEN = $12

DMA Transfer Length Register

VDC_SAT_SRC = $13

VRAM-SAT Source Address Register

VDC_CR_SPR_COLLISION_ENABLE = $0001

Enables sprite collision interrupt.

VDC_CR_SPR_OVERFLOW_ENABLE = $0002

Enables sprite overflow interrupt.

VDC_CR_HBLANK_ENABLE = $0004

Enables horizontal blank interrupt.

VDC_CR_VBLANK_ENABLE = $0008

Enables vertical blank interrupt.

VDC_CR_SPR_ENABLE = $0040

Enables sprites layer.

VDC_CR_BG_ENABLE = $0080

Enables background layer.

VDC_CR_RW_INC_1 = $0000

Read/write address auto-increment by 1 word.

VDC_CR_RW_INC_32 = $0800

Read/write address auto-increment by 32 words.

VDC_CR_RW_INC_64 = $1000

Read/write address auto-increment by 64 words.

VDC_CR_RW_INC_128 = $1800

Read/write address auto-increment by 128 words.

VDC_BG_32x32 = %00000000

32x32 virtual background map.

VDC_BG_64x32 = %00010000

64x32 virtual background map.

VDC_BG_128x32 = %00100000

128x32 virtual background map.

VDC_BG_32x64 = %01000000

32x64 virtual background map.

VDC_BG_64x64 = %01010000

64x64 virtual background map.

VDC_BG_128x64 = %01100000

128x64 virtual background map.

VDC_DMA_SATB_ENABLE = %00000001

Enables VRAM to SATB end of transfer interrupt.

VDC_DMA_VRAM_ENABLE = %00000010

Enables VRAM to VRAM end of transfer interrupt.

VDC_DMA_SRC_INC = %00000000

Source address direction (increment).

VDC_DMA_SRC_DEC = %00000100

Source address direction (decrement).

VDC_DMA_DST_INC = %00000000

Destination address direction (increment).

VDC_DMA_DST_DEC = %00001000

Destination address direction (decrement).

VDC_DMA_SAT_AUTO = %00010000

Enable SAT DMA auto-transfer.

vdc_disp = $20f2

VDC display flag.

vdc_crl = $20f3

Copy of the VDC control register LSB.

vdc_crh = $20f4

Copy of the VDC control register MSB.

vdc_sr = $20f6

Copy of the VDC status register.

vdc_ri = $20f7

Copy of the VDC register index.

VDC_DEFAULT_BG_SIZE = VDC_BG_64x64

Default virtual background map size.

Default tile address.

VDC_DEFAULT_XRES = 256

Default horizontal resolution.

VDC_DEFAULT_SAT_ADDR = $7F00

Default SAT VRAM offset.